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1 rad hard dual 36v precision single-supply, rail-to-rail output, low-power operational amplifiers isl70218seh the isl70218seh is a dual, low-power precision amplifier optimized for single-supply applic ations. this op amp features a common mode input voltage range extending to 0.5v below the v- rail, a rail-rail differential input voltage range, and rail-to-rail output voltage swing, which makes it ideal for single-supply applications where input operation at ground is important. this op amp features low power, low offset voltage, and low temperature drift, making it ideal for applications requiring both high dc accuracy and ac performance. this amplifier is designed to operate over a single supply range of 3v to 36v or a split supply voltage range of +1.8v/-1.2v to 18v. the combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for this amplifier include precision instrumentation, data acquisit ion and precision power supply controls. the isl70218seh is available in a 10 lead hermetic ceramic flatpack and operates over the extended temperature range of -55c to +125c. related literature ? an1653 , ?isl70218srh evaluation board user?s guide? ? an1677 , ?single events effects testing of the isl70218srh, dual 36v rad hard low power operational amplifiers? features ?dla smd# 5962-12222 ? wide single and dual supply range . . . . 3v to 42v, abs. max. ? low current consumption . . . . . . . . . . . . . . . . . . . 850a, typ. ? low input offset voltage . . . . . . . . . . . . . . . . . . . . . 40v, typ. ? rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mv ? rail-to-rail input differential voltage range for comparator applications ? operating temperature range. . . . . . . . . . .-55c to +125c ? below-ground (v-) input capability to -0.5v ? low noise voltage . . . . . . . . . . . . . . . . . . . . . . 5.6nv/ hz, typ. ? low noise current . . . . . . . . . . . . . . . . . . . . . . 355fa/ hz, typ. ? offset voltage temperature drift . . . . . . . . . . . 0.3v/c, typ. ? no phase reversal ? radiation tolerance - sel/seb let th (v s = 18v) . . . . . . . . . 86.4 mev * cm 2 /mg - high dose rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(si) - low dose rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(si) * product capability established by initial characterization. the eh version is acceptance tested on a wafer by wafer basis to 50krad(si) at low dose rate. applications ? precision instruments ? active filter blocks ? data acquisition ? power supply control figure 1. typical application: single-supply, low-side current sense amplifier figure 2. input offset voltage vs input common mode voltage, v s = 15v in- in+ r f r ref + isl70218seh +3v v- v+ r in - 10k ? r in + 10k ? - + 100k ? v ref 100k ? v out load r sense gain = 10 to 36v |v os (v)| input common mode voltage (v) -400 -300 -200 -100 0 100 200 300 400 -16 -15 -14 -13 13 14 15 16 +125c -40c +25c -55c august 24, 2012 fn7957.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl70218seh 2 fn7957.1 august 24, 2012 pin configuration isl70218seh (10 ld flatpack) top view 10 9 8 7 6 2 3 4 5 1 out_a -in_a +in_a nc v- v+ out_b -in_b +in_b nc + - +- pin descriptions pin number pin name equivalent circuit description 1 out_a circuit 2 amplifier a output 2 -in_a circuit 1 amplifier a inverting input 3 +in_a circuit 1 amplifier a non-inverting input 4nc no connect 5 v- circuit 1, 2, 3 negative power supply 6nc no connect 7 +in_b circuit 1 amplifier b non-inverting input 8 -in_b circuit 1 amplifier b inverting input 9 out_b circuit 2 amplifier b output 10 v+ circuit 1, 2, 3 positive power supply v + v - out circuit 2 circuit 1 v + v - circuit 3 in- v + v - in + capacitively triggered esd clamp ordering information ordering number (notes 1, 2) part number temp range (c) package pkg. dwg. # 5962r1222201vxc isl70218sehvf -55 to +125 10 ld flatpack k10.a isl70218sehf/proto isl70218 sehf/proto -55 to +125 10 ld flatpack k10.a 5962r1222201v9a isl70218sehvx -55 to +125 die isl70218sehx/sample isl70218sehvx/sample -55 to +125 die isl70218srhmeval1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device information page for isl70218seh . for more information on msl, please see tech brief tb363 .
isl70218seh 3 fn7957.1 august 24, 2012 absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42v maximum supply voltage (let = 86.4 mev ? cm 2 /mg) . . . . . . . . . . . . . 36v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum differential input voltage . . . . . . . . . . . . . . .v - - 0.5v to v + + 0.5v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .v - - 0.5v to v + + 0.5v max/min input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma output short-circuit duration (1 output at a time) . . . . . . . . . . . . . . indefinite esd tolerance human body model (tested per mil-prf-883 3015.7). . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 300v charged device model (tested per cdm-22ci0id) . . . . . . . . . . . . . . 750v di-electrically isolated pr40 process . . . . . . . . . . . . . . . . . . . latch-up free thermal resistance (typical) ja (c/w) jc (c/w) 10 ld flatpack package (notes 3, 4). . . . . 130 20 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient operating temperature range . . . . . . . . . . . . . .-55c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . .+150c supply voltage . . . . . . . . . . . . . . . . . . . . . . 3v (+1.8v/-1.2v) to 30v (15v) caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. for jc , the ?case temp? location is the center of the package underside. electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c. parameter description conditions min (note 5) typ max (note 5) unit v os offset voltage 40 230 v 290 v tcv os offset voltage drift 0.3 1.4 v/ c v os input offset voltage match channel to channel 44 280 v 365 v i os input offset current -50 4 50 na -75 75 na i b input bias current -575 -230 na -800 na v cmir common mode input voltage range guaranteed by cmrr test (v-) - 0.5 (v+) - 1.8 v v- (v+) - 1.8 v cmrr common-mode rejection ratio v cm = v - to v + -1.8v 100 118 db v cm = v - to v + -1.8v 97 db psrr power supply rejection ratio v s = 3v to 40v, v cmir = valid input voltage 105 124 db 100 db a vol open-loop gain r l = 10k to ground v o = -13v to +13v 120 130 db 115 db v oh output voltage high, v + to v out r l = 10k 110 mv 120 mv v ol output voltage low, v out to v - r l = 10k 70 mv 80 mv i s supply current/amplifier 0.85 1.1 ma 1.4 ma i s+ source current capability 10 ma i s- sink current capability 10 ma v supply supply voltage range guaranteed by psrr 3 40 v
isl70218seh 4 fn7957.1 august 24, 2012 ac specifications gbw gain bandwidth product a cl = 101, v out = 100mv p-p ; r l = 2k 4mhz e np-p voltage noise 0.1hz to 10hz, v s = 18v 300 nv p-p e n voltage noise density f = 10hz, v s = 18v 8.5 nv/ hz e n voltage noise density f = 100hz, v s = 18v 5.8 nv/ hz e n voltage noise density f = 1khz, v s = 18v 5.6 nv/ hz e n voltage noise density f = 10khz, v s = 18v 5.6 nv/ hz in current noise density f = 1khz, v s = 18v 355 fa/ hz thd + n total harmonic distortion + noise 1khz, g = 1, v o = 3.5v rms , r l = 10k 0.0003 % transient response sr slew rate a v = 1, r l = 2k , v o = 10v p-p 1.0 1.2 v/s 0.4 v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 100 200 ns 400 ns fall time 90% to 10% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l = 2k to v cm 100 230 ns 400 ns t s settling time to 0.01% 10v step; 10% to v out a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 8.5 s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 5% 35 % os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 5% 35 % electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over a total ionizing dose of 100krad(si) with exposure at a high dose rate of 50 - 300krad(si)/s; and over a total ionizing dose of 50krad( si) with exposure at a low dose rate of <10mrad(si)/s. parameter description conditions min (note 5) typ max (note 5) unit v os offset voltage 40 230 v 290 v tcv os offset voltage drift 0.3 1.4 v/ c v os input offset voltage match channel to channel 44 280 v 365 v i os input offset current -50 4 50 na -75 75 na i b input bias current -575 -230 na -1500 na v cmir common mode input voltage range guaranteed by cmrr test (v-) - 0.5 (v+) -1.8 v v- (v+) - 1.8 v cmrr common-mode rejection ratio v cm = v - to v + -1.8v 100 118 db v cm = v - to v + -1.8v 97 db electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c. (continued) parameter description conditions min (note 5) typ max (note 5) unit
isl70218seh 5 fn7957.1 august 24, 2012 psrr power supply rejection ratio v s = 3v to 40v, v cmir = valid input voltage 105 124 db 100 db a vol open-loop gain r l = 10k to ground v o = -13v to +13v 120 130 db 115 db v oh output voltage high, v + to v out r l = 10k 110 mv 120 mv v ol output voltage low, v out to v - r l = 10k 70 mv 80 mv i s supply current/amplifier 0.85 1.1 ma 1.4 ma i s+ source current capability 10 ma i s- sink current capability 10 ma v supply supply voltage range guaranteed by psrr 3 40 v ac specifications gbw gain bandwidth product a cl = 101, v out = 100mv p-p ; r l = 2k 4mhz e np-p voltage noise 0.1hz to 10hz, v s = 18v 300 nv p-p e n voltage noise density f = 10hz, v s = 18v 8.5 nv/ hz e n voltage noise density f = 100hz, v s = 18v 5.8 nv/ hz e n voltage noise density f = 1khz, v s = 18v 5.6 nv/ hz e n voltage noise density f = 10khz, v s = 18v 5.6 nv/ hz in current noise density f = 1khz, v s = 18v 355 fa/ hz thd + n total harmonic distortion + noise 1khz, g = 1, v o = 3.5v rms , r l = 10k 0.0003 % transient response sr slew rate a v = 1, r l = 2k , v o = 10v p-p 1.0 1.2 v/s 0.4 v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 100 230 ns 400 ns fall time 90% to 10% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l = 2k to v cm 100 200 ns 400 ns t s settling time to 0.01% 10v step; 10% to v out a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 8.5 s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 5% 35 % os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 5% 35 % electrical specifications v s 15v, v cm = 0, v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply over a total ionizing dose of 100krad(si) with exposure at a high dose rate of 50 - 300krad(si)/s; and over a total ionizing dose of 50krad( si) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter description conditions min (note 5) typ max (note 5) unit
isl70218seh 6 fn7957.1 august 24, 2012 electrical specifications v s 5v, v cm = 0, v o = 0v, t a = +25c, unless otherwise noted. boldface limits apply over the operating temperature range, -55c to +125c. parameter description conditions min (note 5) typ max (note 5) unit v os offset voltage 40 v v os input offset voltage match channel to channel 44 v i os input offset current 4 na i b input bias current -230 na v cmir common mode input voltage range guaranteed by cmrr test (v-) - 0.5 (v+) - 1.8 v v- (v+) - 1.8 v cmrr common-mode rejection ratio v cm = v - - 0.5v to v + - 1.8 v cm = v - to v + -1.8v 117 db psrr power supply rejection ratio v s = 3v to 40v, v cmir = valid input voltage 124 db a vol open-loop gain r l = 10k to ground v o = -3v to +3v 130 db v oh output voltage high, v + to v out r l = 10k 65 mv 70 mv v ol output voltage low, v out to v - r l = 10k 38 mv 45 mv i s supply current/amplifier 0.85 ma i s+ source current capability 8 ma i s- sink current capability 8 ma ac specifications gbw gain bandwidth product 3.2 mhz e np-p voltage noise 0.1hz to 10hz 320 nv p-p e n voltage noise density f = 10hz 9 nv/ hz e n voltage noise density f = 100hz 5.7 nv/ hz e n voltage noise density f = 1khz 5.5 nv/ hz e n voltage noise density f = 10khz 5.5 nv/ hz in current noise density f = 1khz 380 fa/ hz thd + n total harmonic distortion + noise 1khz, g = 1, v o = 1.25v rms , r l =10k 0.0003 % transient response sr slew rate a v = 1, r l = 2k , v o = 4v p-p 1 v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l =2k to v cm 100 ns fall time 90% to 10% of v out a v = 1, v out = 100mv p-p , r f = 0 , r l = 2k to v cm 100 ns t s settling time to 0.01% 4v step; 10% to v out a v = 1, v out = 4v p-p , r f = 0 r l =2k to v cm 4s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 5% os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k to v cm 5% note: 5. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
isl70218seh 7 fn7957.1 august 24, 2012 high dose rate post radiation characteristics v s 15v, v cm = 0v, v o = 0v, r l = open, t a = +25c, unless otherwise noted. this data is typical test data post radiation exposure at a rate of 50 to 300rad(si)/s. this data is intended to show typical p arameter shifts due to high dose rate radiation. these ar e not limits nor are they guaranteed. parameter description conditions 50k rad 75k rad 100k rad unit v os offset voltage 35 35 35 v i os input offset current 2 3 5 na i b input bias current 200 400 575 na cmrr common-mode rejection ration v cm = -13v to +13v 129 128 127 db psrr power supply rejection ratio v s = 2.25v to 15v 130 130 130 db a vol open-loop gain v o = -13v to +13v r l = 10k to ground 131.6 131.1 131.1 db v oh output voltage high v + to v out r l = 10k to ground 71 74 76 mv v ol output voltage low v out to v - r l = 10k to ground 54 57 59 mv i s supply current/amplifier 830 830 830 a transient response sr slew rate a v = 10, r l = 2k , v o = 4v p-p 1.24 1.23 1.22 v/s low dose rate post radiation characteristics v s 15v, v cm = 0v, v o = 0v, r l = open, t a = +25c, unless otherwise noted. this data is typical test data post radiation exposure at a rate of 10mrad(si)/s. this data is intended to show typical paramet er shifts due to low dose rate radiation. these are no t limits nor are they guaranteed. parameter description conditions 10k rad 20k rad 50k rad unit v os offset voltage 20 20 20 v i os input offset current 6 8 10 na i b input bias current 300 500 1200 na i s supply current/amplifier 650 625 615 a
isl70218seh 8 fn7957.1 august 24, 2012 typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. figure 3. v os vs temperature figure 4. input offset voltage vs input common mode voltage, v s = 15v figure 5. i bias vs v s figure 6. i bias vs temperature vs supply figure 7. cmrr vs temperature, v s = 15v figure 8. cmrr vs temperature, v s = 5v 0 10 20 30 40 50 60 70 80 90 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 v o s ( v ) temperature (c) v s = 5v v s = 15v |v os (v)| input common mode voltage (v) -400 -300 -200 -100 0 100 200 300 400 -16 -15 -14 -13 13 14 15 16 +125c -40c +25c -55c i bias (na) -500 -450 -400 -350 -300 -250 -200 -150 -100 -50 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 v s (v) i bias (na) -400 -350 -300 -250 -200 -150 temperature (c) -60 -20 0 20 40 60 80 100 120 v s = +40v -40 140 v s = +3.0v v s = +4.5v v s = +10v v s = +30v temperature (c) cmrr (db) 110 112 114 116 118 120 122 124 126 128 130 132 -60 -40 -20 0 20 40 60 80 100 120 140 160 channel-a channel-b temperature (c) cmrr (db) 110 112 114 116 118 120 122 124 126 128 130 132 -60 -40 -20 0 20 40 60 80 100 120 140 160 channel-a channel-b
isl70218seh 9 fn7957.1 august 24, 2012 figure 9. cmrr vs frequency, v s = 15v figure 10. psrr vs temperature, v s = 15v figure 11. psrr vs frequency, v s = 15v figure 12. psrr vs frequency, v s = 5v figure 13. open-loop gain, phase vs frequency, v s = 15v figure 14. frequency response vs closed loop gain typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) c m r r ( d b ) frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 1m 1 10 100 1k 10k 100k 1m 10m 100m 1g 0.1 0.01 v s = 15v simulation -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) 100 105 110 115 120 125 130 135 140 p s r r ( d b ) 10 100 1k 10k 100k 1m 10m p s r r ( db ) frequency (hz) -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 v s = 15v c l = 4pf v cm = 1v p-p r l = 10k a v = 1 psrr- psrr+ 10 100 1k 10k 100k 1m 10m p s r r ( db ) frequency (hz) -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 v s = 5v c l = 4pf v cm = 1v p-p r l = 10k a v = 1 psrr- psrr+ -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 1m 1 10 100 1k 10k 100k 1m 10m100m 1g g a i n ( db ) frequency (hz) 0.1 v s = 15v r l = 1m ? 0.01 gain phase -10 0 10 20 30 40 50 60 70 1k 10k 100k 1m 10m g a i n ( db ) frequency (hz) a cl = 1 a cl = 10 a cl = 100 a cl = 1000 100 v s = 5v & 15v c l = 4pf v out = 100mv p-p r l = 2k r f = 10k ? , r g = 100 ? r f = 10k ? , r g = 1k ? r f = 0, r g = r f = 10k ? , r g = 10 ?
isl70218seh 10 fn7957.1 august 24, 2012 figure 15. gain vs frequency vs r l , v s = 15v figure 16. gain vs frequency vs r l , v s = 5v figure 17. gain vs frequency vs output voltage figure 18. gain vs frequency vs supply voltage figure 19. output overhead voltage vs temperature, v s = 15v, r l =10k figure 20. output overhead voltage vs temperature, v s = 5v, r l = 10k typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 v s = 15v a v = +1 v out = 100mv p-p c l = 4pf r l = 1k r l = 499 r l = 100 r l = 49.9 r l = open, 100k, 10k frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 v s = 5v a v = +1 v out = 100mv p-p c l = 4pf r l = open, 100k, 10k r l = 1k r l = 499 r l = 100 r l = 49.9 frequency (hz) normalized gain (db) 100k 1m 10m 10k 1k -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 v out = 1v p-p v out = 500mv p-p v out = 10mv p-p v out = 50mv p-p v out = 100mv p-p v s = 5v a v = +1 r l = inf c l = 4pf normalized gain (db) frequency (hz) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 100 1k 10k 100k 1m 10m c l = 4pf r l = 10k a v = +1 v out = 100mv p-p v s = 15v v s = 1.5v v s = 5v 40 50 60 70 80 90 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 v o h a n d v o l ( m v ) temperature (c) v oh v s = 15v r l = 10k v ol -60 -40 -20 0 20 40 60 80 100 120 140 160 v o h a n d v o l ( m v ) temperature (c) v oh v s = 5v r l = 10k v ol 20 22 24 26 28 30 32 34 36 38 40 42
isl70218seh 11 fn7957.1 august 24, 2012 figure 21. output overhead voltage high vs load current, v s = 5v and 15v figure 22. output overhead voltage low vs load current, v s = 5v and 15v figure 23. output voltage swing vs load current, v s = 15v figure 24. output voltage swing vs load current, v s = 5v figure 25. supply current vs temperature vs supply voltage figure 26. supply current vs supply voltage typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) v + - v o h ( v ) load current (ma) 0.001 0.01 0.1 1.0 0.001 0.01 0.1 1.0 10 v s = 5v and 15v +125c +25c -55c load current (ma) 0.001 0.01 0.1 1.0 0.001 0.01 0.1 1.0 10 v s = 5v and 15v v o l - v - ( v ) +125c +25c -55c v o h 0 v o l i-force (ma) 11 12 13 14 15 -15 -14 -13 -12 -11 22 18 16 14 12 10 8 6 4 2 10 -10 0c -40c +25c +75c +125c 20 24 -55c v s = 15v a v = 2 v in = 7.5v-dc r f = r g = 100k v o h v o l i-force (ma) 1 2 3 4 5 -5 -4 -3 -2 -1 v s = 5v a v = 2 v in = 2.5v-dc r f = r g = 100k 0c -40c +25c +75c +125c -55c 022 18 16 14 12 10 8 6 4 22024 temperature (c) current (a) 400 600 800 1000 1200 1400 1600 -60 -40 -20 0 20 40 60 80 100 120 140 160 v s = 2.25v v s = 15v v s = 21v v supply (v) 0 2 4 6 8 1012141618202224262830323436384042 0 100 200 300 400 500 600 700 800 900 1000 1100 i s u p p l y p e r a m p l i f i e r ( a )
isl70218seh 12 fn7957.1 august 24, 2012 figure 27. input noise voltage (en) and current (in) vs frequency, v s = 18v figure 28. input noise voltage (en) and current (in) vs frequency, v s = 5v figure 29. input noise voltage 0.1hz to 10hz, v s = 18v figure 30. input noise voltage 0.1hz to 10hz, v s = 5v figure 31. thd+n vs frequency vs temperature, a v = 1, 10, r l = 2k figure 32. thd+n vs frequency vs temperature, a v = 1, 10, r l = 10k typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) 0.1 1 10 100 0.1 1 10 100 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( f a / h z ) v s = 18v input noise voltage input noise current 0.1 1 10 100 0.1 1 10 100 0.1 1 10 100 1k 10k 100k i n p u t n o i s e v o l t a g e ( n v / h z ) frequency (hz) i n p u t n o i s e c u r r e n t ( f a / h z ) input noise current v s = 5v input noise voltage i n p u t n o i s e v o l t a g e ( n v ) 012345678910 time (s) -500 -400 -300 -200 -100 0 100 200 300 400 500 v s = 18v a v = 10k i n p u t n o i s e v o l t a g e ( n v ) 012345678910 time (s) -500 -400 -300 -200 -100 0 100 200 300 400 500 v s = 5v a v = 10k 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k t h d + n ( % ) frequency (hz) a v = 1 a v = 10 v s = 15v c l = 4pf v out = 10v p-p r l = 2k c-weighted 22hz to 500khz +25c -55c +25c +125c -55c +125c 0.0001 0.001 0.01 0.1 10 100 1k 10k 100k t h d + n ( % ) frequency (hz) a v = 10 v s = 15v c l = 4pf v out = 10v p-p r l = 10k c-weighted 22hz to 500khz +125c +25c -55c a v = 1 -55c +25c +125c
isl70218seh 13 fn7957.1 august 24, 2012 figure 33. thd+n vs output voltage (v out ) vs temperature, a v = 1, 10, r l = 2k figure 34. thd+n vs output voltage (v out ) vs temperature, a v = 1, 10, r l = 10k figure 35. large signal 10v step response, v s = 15v figure 36. large signal 4v step response, v s = 5v figure 37. small signal transient response, v s = 5v, 15v figure 38. no phase reversal typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) 0.0001 0.001 0.01 0.1 1.0 0 5 10 15 20 25 30 v out (v p-p ) t h d + n ( % ) a v = 1 c-weighted 22hz to 22khz a v = 10 -55c v s = 15v c l = 4pf f = 1khz r l = 2k -55c +125c +25c +125c +25c 0.0001 0.001 0.01 0.1 1.0 0 5 10 15 20 25 30 v out (v p-p ) t h d + n ( % ) a v = 1 a v = 10 c-weighted 22hz to 22khz v s = 15v c l = 4pf f = 1khz r l = 10k +125c +25c -55c +25c -55c +125c -6 -4 -2 0 2 4 6 0 102030405060708090100 v o u t ( v ) time (s) v s = 15v a v = 1 r l = 2k c l = 4pf 0 102030405060708090100 v o u t ( v ) time (s) -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 v s = 5v a v = 1 r l = 2k c l = 4pf v o u t ( v ) time (s) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2 v s = 15v a v = 1 r l = 2k c l = 4pf v s = 5v and -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 01234 i n p u t a n d o u t p u t ( v ) time (ms) v s = 5v v in = 5.9v input output
isl70218seh 14 fn7957.1 august 24, 2012 figure 39. positive output overload response time, v s = 15v figure 40. negative output overload response time, v s = 15v figure 41. positive output overload response time, v s = 5v figure 42. negative output overload response time, v s = 5v figure 43. output impedance vs frequency, v s = 15v figure 44. output impedance vs frequency, v s = 5v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) o u t p u t ( v ) i n p u t ( m v ) time (s) 0 4 8 12 16 20 0 40 80 120 160 200 0 4 8 1216202428323640 v s = 15v a v = 100 v in = 100mv p-p overdrive = 1v r l = 10k output input o u t p u t ( v ) i n p u t ( m v ) time (s) -20 -16 -12 -8 -4 0 -200 -160 -120 -80 -40 0 0 4 8 12 16 20 24 28 32 36 40 v s = 15v a v = 100 v in = 100mv p-p overdrive = 1v r l = 10k output input o u t p u t ( v ) i n p u t ( m v ) time (s) 0 1 2 3 4 5 6 0 10 20 30 40 50 60 0 4 8 1216202428323640 v s = 5v a v = 100 v in = 50mv p-p overdrive = 1v r l = 10k input output o u t p u t ( v ) i n p u t ( m v ) time (s) 0 4 8 12 16 20 24 28 32 36 40 -6 -5 -4 -3 -2 -1 0 -60 -50 -40 -30 -20 -10 0 v s = 5v a v = 100 v in = 50mv p-p overdrive = 1v r l = 10k output input 0.01 0.10 1 10 100 10 100 1k 10k 100k 1m 10m z o u t ( ? ) frequency (hz) 1 v s = 15v a v = 1 a v = 10 a v = 100 0.01 0.10 1 10 100 10 100 1k 10k 100k 1m 10m z o u t ( ? ) frequency (hz) 1 v s = 5v a v = 1 a v = 10 a v = 100
isl70218seh 15 fn7957.1 august 24, 2012 figure 45. overshoot vs capacitive load, v s = 15v figure 46. overshoot vs capacitive load, v s =5v figure 47. imax output voltage vs frequency fig ure 48. short circuit current vs temperature, v s = 15v typical performance curves v s = 15v, v cm = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) o v e r s h o o t ( % ) load capacitance (nf) 0 10 20 30 40 50 60 0.001 0.010 0.100 1 10 100 v s = 15v v out = 100mv p-p a v = 10 a v = 1 a v = -1 o v e r s h o o t ( % ) load capacitance (nf) 0 10 20 30 40 50 60 0.001 0.01 0.1 1 10 100 v s = 5v v out = 100mv p-p a v = 10 a v = 1 a v = -1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1k 10k 100k 1m v ou t ( v p - p ) frequency (hz) v s = 15v a v = 1 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) 10 12 14 16 18 20 22 24 26 28 30 i s c ( m a ) i sc -source v s = 15v r l = 10k i sc -sink
isl70218seh 16 fn7957.1 august 24, 2012 applications information functional description the isl70218seh is a dual, 3.2m hz, single or dual supply, rail-to-rail output amplifier with a common mode input voltage range extending to a range of 0. 5v below the v- rail. the input stage is optimized for precisio n sensing of ground-referenced signals in single-supply applicatio ns. the input stage is able to handle large input differential vo ltages without phase inversion, making this amplifier suitable for high-voltage comparator applications. the bipolar design fe atures high open loop gain and excellent dc input and output temperature stability. this op amp features very low quiescent current of 850a, and low temperature drift. the device is fabricated in a new precision 40v complementary bipolar di process and is immune from latch-up for up to a 36v supply range. operating voltage range the op amp is designed to operate over a single supply range of 3v to 36v or a split supply voltage range of +1.8v/-1.2v to 18v. the device is fully characterized at 30v (15v). both dc and ac performance remain virtually unchanged over the complete operating voltage range. parame ter variation with operating voltage is shown in the ?typical performance curves? beginning on page 8. the input common mode voltage to the v+ rail (v+ - 1.8v over the full temperature range) may lim it amplifier operation when operating from split v+ and v- supplies. figure 4 shows the common mode input voltage range variation over temperature. input stage performance the isl70218seh pnp input stag e has a common mode input range extending up to 0.5v below ground at +25c. full amplifier performance is guaranteed for inpu t voltage down to ground (v-) over the -55c to +125c temperature range. for common mode voltages down to -0.5v below grou nd (v-), the amplifiers are fully functional, but performance degr ades slightly over the full temperature range. this featur e provides excellent cmrr, ac performance, and dc accuracy when amplifying low-level, ground-referenced signals. the input stage has a maximum input differential voltage equal to a diode drop greater than th e supply voltage and does not contain the back-to-back input pr otection diodes found on many similar amplifiers. this feature enables the device to function as a precision comparator by maintaining very high input impedance for high-voltage differential input comparator voltages. the high differential input impedance also enables the device to operate reliably in large signal pulse applications, without the need for anti-paral lel clamp diodes required on mosfet and most bipolar inpu t stage op amps. thus, input signal distortion caused by nonlinear clamps under high slew rate conditions is avoided. in applications in which one or both amplifier input terminals is at risk of exposure to volt ages beyond the supply rails, current-limiting resistors may be needed at each input terminal (see figure 49, r in +, r in -) to limit current through the power-supply esd diodes to 20ma. output drive capability the bipolar rail-to-rail output stag e features low saturation levels that enable an output voltage swing to less than 15mv when the total output load (including feedback resistance) is held below 50a (figures 21 and 22). wi th 15v supplies, this can be achieved by using feedback resistor values >300k ? . the output stage is internally current limited. output current limit over temperature is shown in figures 23 and 24. the amplifiers can withstand a short circuit to ei ther rail as long as the power dissipation limits are not exceeded. this applies to only one amplifier at a time fo r the dual op amp. continuous operation under these conditions may degrade long-term reliability. the amplifiers perform well when driving capacitive loads (figures 45 and 46). the unity gain, voltage follower (buffer) configuration provides the high est bandwidth but is also the most sensitive to ringing produced by load capacitance found in bnc cables. unity gain overshoot is limited to 35% at capacitance values to 0.33nf. at gains of 10 and higher, the device is capable of driving more than 10nf without significant overshoot. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the isl70218seh is immune to output phase reversal out to 0.5v beyond the rail (v abs max ) limit (figure 38). single channel usage the isl70218seh is a dual op amp. if the application requires only one channel, the user must configure the unused channel to prevent it from oscillating. the unused channel oscillates if the input and output pins are floating. this results in higher-than-expected supply currents and possible noise injection into the channel being used. the proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input (figure 50). figure 49. input esd diode current limiting - + r in - r l v in - v+ v- r in + v in + r f r g figure 50. preventing oscillations in unused channels - +
isl70218seh 17 fn7957.1 august 24, 2012 power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions , or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1: where ?pd maxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?t max = maximum ambient temperature ? ja = thermal resistance of the package pd max for each amplifier can be calculated using equation 2: where ?pd max = maximum power dissipation of one amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of one amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance t jmax t max ja xpd maxtotal + = (eq. 1) pd max v s i qmax v s ( - v outmax ) v outmax r l ------------------------ + = (eq. 2)
isl70218seh 18 fn7957.1 august 24, 2012 package characteristics weight of packaged device 0. 4029 grams (typical) lid characteristics finish: gold case isolation to any lead: 20 x 10 9 ? (min) die characteristics die dimensions 1565m x 2125m (62mils x 84mils) thickness: 355m 25m (14 mils 1 mil) interface materials glassivation type: nitrox thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon process dielectrically isolated complementary bipolar - pr40 assembly related information substrate potential floating additional information worst case current density < 2 x 10 5 a/cm 2 metallization mask layout place holder v+ out_b -in_b +in_b v- +in_a -in_a out_a
isl70218seh 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7957.1 august 24, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl70218seh to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php table 1. die layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad out_a 1 16.5 1670 70 70 1 -in_a 6 -3 1015 70 70 1 +in_a 7 -3 771 70 70 1 v- 8 0 070701 +in_b 12 1287 719.5 70 70 1 -in_b 11 1287 963.5 70 70 1 out_b 10 1267.5 1115.5 70 70 1 v+ 9 1284 1746.5 70 70 1 note: 6. origin of coordinates is the centroid of pad 8. revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change august 24, 2012 fn7957.1 1. electrical specification tables (pages 3-6) , added specs on overshoot and rise/fall times. 2. page 3 - added abs max in a non radiation environment changed esd hbm from 3kv to 2kv changed esd cdm from 2kv to 750v february 16, 2012 fn7957.0 initial release
isl70218seh 20 fn7957.1 august 24, 2012 ceramic metal seal flat pack packages (flatpack) notes: 1. index area: a notch or a pin one iden tification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. the manufacturer?s identification sha ll not be used as a pin one identi- fication mark. alternately, a tab (dim ension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m ap- plies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m shall be m easured at the centroid of the fin- ished lead surfaces, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the menis- cus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and toleranci ng per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m d k10.a mil-std-1835 cdfp3-f10 (f-4a, configuration b) 10 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.290 - 7.37 3 e 0.240 0.260 6.10 6.60 - e1 -0.280 -7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n10 10- rev. 0 3/07

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